LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fsm IS
    PORT(clk    : in STD_LOGIC;
         reset  : in STD_LOGIC;
         input  : in STD_LOGIC;
         output : out STD_LOGIC);
 END fsm;
 
 ARCHITECTURE fsm_Moore OF fsm IS
        TYPE STATE_TYPE IS (s0, s1);
        SIGNAL state : STATE_TYPE;
  BEGIN
       PROCESS (clk)
       BEGIN
           IF reset = '1' THEN
                 state <= s0; 
             ELSE IF (clk'EVENT AND clk = '1')  THEN
               CASE state IS
                   WHEN s0 =>
                        state <= s1;
                   WHEN s1 =>
                       IF input = '1' THEN
                            state <= s0;
                        ELSE
                            state <= s1;
                        END IF;
                END CASE;
              END IF;
            END IF;
        END PROCESS;
        
        output <= '1'  WHEN state = s1 ELSE '0';
  END fsm_Moore;                
                            
                        
